... | ... |
@@ -89,6 +89,18 @@ inline static int tsl(fl_lock_t* lock) |
89 | 89 |
: "r"(1), "r" (lock) : "memory" |
90 | 90 |
); |
91 | 91 |
|
92 |
+#elif defined __CPU_ppc |
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93 |
+ asm volatile( |
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+ "1: lwarx %0, 0, %2\n\t" |
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+ " cmpwi %0, 0\n\t" |
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+ " bne 0f\n\t" |
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+ " stwcx. %1, 0, %2\n\t" |
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+ " bne- 1b\n\t" |
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+ "0:\n\t" |
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+ : "=r" (val) |
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+ : "r"(1), "b" (lock) : |
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+ "memory", "cc" |
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+ ); |
|
92 | 104 |
#else |
93 | 105 |
#error "unknown arhitecture" |
94 | 106 |
#endif |
... | ... |
@@ -142,6 +154,15 @@ inline static void release_lock(fl_lock_t* lock) |
142 | 154 |
: "r"(0), "r"(lock) |
143 | 155 |
: "memory" |
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); |
157 |
+#elif defined __CPU_ppc |
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+ asm volatile( |
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+ "sync\n\t" |
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+ "stw %0, 0(%1)\n\t" |
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+ : /* no output */ |
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+ : "r"(0), "b" (lock) |
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+ : "memory" |
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+ ); |
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+ *lock = 0; |
|
145 | 166 |
#else |
146 | 167 |
#error "unknown arhitecture" |
147 | 168 |
#endif |