deleted file mode 100644

@@ -1,184 +0,0 @@

-/* 

- * Copyright (C) 2006 iptelorg GmbH

- *

- * Permission to use, copy, modify, and distribute this software for any

- * purpose with or without fee is hereby granted, provided that the above

- * copyright notice and this permission notice appear in all copies.

- *

- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES

- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF

- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR

- * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES

- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN

- * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF

- * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.

- */

-

-/*!

- * \file

- * \brief Kamailio core :: Atomic operations and memory barriers

- * Copyright (C) 2006 iptelorg GmbH

- * \ingroup core

- * Module: \ref core

- * See \ref atomic

- */

-

-/**

- * \page atomicops  Atomic operations and memory barriers

- *

- *  WARNING: atomic ops do not include memory barriers

- *  

- *  memory barriers:

- *  ----------------

- *

- *  void membar();        - memory barrier (load & store)

- *  void membar_read()    - load (read) memory barrier

- *  void membar_write()   - store (write) memory barrier

- *  void membar_depends() - read depends memory barrier, needed before using

- *                          the contents of a pointer (for now is needed only

- *                          on Alpha so on all other CPUs it will be a no-op)

- *                          For more info see: 

- *                          http://lse.sourceforge.net/locking/wmbdd.html

- *                          http://www.linuxjournal.com/article/8212

- *

- *  void membar_enter_lock() - memory barrier function that should be 

- *                             called after a lock operation (where lock is

- *                             an asm inline function that uses atomic store

- *                             operation on the lock var.). It is at most

- *                             a StoreStore|StoreLoad barrier, but could also

- *                             be empty if an atomic op implies a memory 

- *                             barrier on the specific arhitecture.

- *                             Example usage: 

- *                               raw_lock(l); membar_enter_lock(); ...

- *  void membar_leave_lock() - memory barrier function that should be called 

- *                             before an unlock operation (where unlock is an

- *                             asm inline function that uses at least an atomic

- *                             store to on the lock var.). It is at most a 

- *                             LoadStore|StoreStore barrier (but could also be

- *                             empty, see above).

- *                             Example: raw_lock(l); membar_enter_lock(); ..

- *                                      ... critical section ...

- *                                      membar_leave_lock(); raw_unlock(l);

- *  void membar_atomic_op() - memory barrier that should be called if a memory

- *                            barrier is needed immediately after or 

- *                            immediately before an atomic operation

- *                            (for example: atomic_inc(&i); membar_atomic_op()

- *                               instead of atomic_inc(&i); membar()).

- *                            atomic_op means every atomic operation except get

- *                            and set (for them use membar_atomic_setget()).

- *                            Using membar_atomic_op() instead of membar() in

- *                            these cases will generate faster code on some

- *                            architectures (for now x86 and x86_64), where 

- *                            atomic operations act also as memory barriers.

- *                            Note that mb_atomic_<OP>(...) is equivalent to

- *                            membar_atomic_op(); atomic_<OP>(...) and in this

- *                            case the first form is preferred).

- * void membar_atomic_setget() - same as above but for atomic_set and 

- *                            atomic_get (and not for any other atomic op.,

- *                            including atomic_get_and_set, for them use

- *                            membar_atomic_op()).

- *                            Note that mb_atomic_{get,set}(&i) is equivalent 

- *                            and preferred to membar_atomic_setget(); 

- *                            atomic_{get,set}(&i) (it will generate faster

- *                            code on x86 and x86_64).

- * void membar_read_atomic_op() - like membar_atomic_op(), but acts only as

- *                             a read barrier.

- * void membar_read_atomic_setget() - like membar_atomic_setget() but acts only

- *                            as a read barrier.

- * void membar_write_atomic_op() - like membar_atomic_op(), but acts only as

- *                            a write barrier.

- * void membar_write_atomic_setget() - like membar_atomic_setget() but acts 

- *                            only as a write barrier.

- *

- *

- *  Note: - properly using memory barriers is tricky, in general try not to 

- *        depend on them. Locks include memory barriers, so you don't need

- *        them for writes/load already protected by locks.

- *        - membar_enter_lock() and membar_leave_lock() are needed only if

- *        you implement your own locks using atomic ops (ser locks have the

- *        membars included)

- *

- * atomic operations:

- * ------------------

- *  type: atomic_t

- *

- * not including memory barriers:

- *

- *  void atomic_set(atomic_t* v, int i)      - v->val=i

- *  int atomic_get(atomic_t* v)              - return v->val

- *  int atomic_get_and_set(atomic_t *v, i)   - return old v->val, v->val=i

- *  void atomic_inc(atomic_t* v)

- *  void atomic_dec(atomic_t* v)

- *  int atomic_inc_and_test(atomic_t* v)     - returns 1 if the result is 0

- *  int atomic_dec_and_test(atomic_t* v)     - returns 1 if the result is 0

- *  void atomic_or (atomic_t* v, int mask)   - v->val|=mask 

- *  void atomic_and(atomic_t* v, int mask)   - v->val&=mask

- *  int atomic_add(atomic_t* v, int i)       - v->val+=i; return v->val

- *  int atomic_cmpxchg(atomic_t* v, o, n)    - r=v->val; if (r==o) v->val=n;

- *                                             return r (old value)

- *

- * 

- * same ops, but with builtin memory barriers:

- *

- *  void mb_atomic_set(atomic_t* v, int i)      -  v->val=i

- *  int mb_atomic_get(atomic_t* v)              -  return v->val

- *  int mb_atomic_get_and_set(atomic_t *v, i)   -  return old v->val, v->val=i

- *  void mb_atomic_inc(atomic_t* v)

- *  void mb_atomic_dec(atomic_t* v)

- *  int mb_atomic_inc_and_test(atomic_t* v)  - returns 1 if the result is 0

- *  int mb_atomic_dec_and_test(atomic_t* v)  - returns 1 if the result is 0

- *  void mb_atomic_or(atomic_t* v, int mask - v->val|=mask 

- *  void mb_atomic_and(atomic_t* v, int mask)- v->val&=mask

- *  int mb_atomic_add(atomic_t* v, int i)    - v->val+=i; return v->val

- *  int mb_atomic_cmpxchg(atomic_t* v, o, n) - r=v->val; if (r==o) v->val=n;

- *                                             return r (old value)

- *

- *  Same operations are available for int and long. The functions are named

- *   after the following rules:

- *     - add an int or long  suffix to the correspondent atomic function

- *     -  volatile int* or volatile long* replace atomic_t* in the functions

- *        declarations

- *     -  long and int replace the parameter type (if the function has an extra

- *        parameter) and the return value

- *  E.g.:

- *    long atomic_get_long(volatile long* v)

- *    int atomic_get_int( volatile int* v)

- *    long atomic_get_and_set(volatile long* v, long l)

- *    int atomic_get_and_set(volatile int* v, int i)

- *

- * Config defines:   CC_GCC_LIKE_ASM  - the compiler support gcc style

- *                     inline asm

- *                   NOSMP - the code will be a little faster, but not SMP

- *                            safe

- *                   __CPU_i386, __CPU_x86_64, X86_OOSTORE - see 

- *                       atomic/atomic_x86.h

- *                   __CPU_mips, __CPU_mips2, __CPU_mips64, MIPS_HAS_LLSC - see

- *                       atomic/atomic_mip2.h

- *                   __CPU_ppc, __CPU_ppc64 - see atomic/atomic_ppc.h

- *                   __CPU_sparc - see atomic/atomic_sparc.h

- *                   __CPU_sparc64, SPARC64_MODE - see atomic/atomic_sparc64.h

- *                   __CPU_arm, __CPU_arm6 - see atomic/atomic_arm.h

- *                   __CPU_alpha - see atomic/atomic_alpha.h

- */

-/* 

- * History:

- * --------

- *  2006-03-08  created by andrei

- *  2007-05-13  moved some of the decl. and includes into atomic_common.h and 

- *               atomic_native.h (andrei)

- */

-#ifndef __atomic_ops

-#define __atomic_ops

-

-#include "atomic/atomic_common.h"

-

-#include "atomic/atomic_native.h"

-

-/*! \brief if no native operations, emulate them using locks */

-#if  ! defined HAVE_ASM_INLINE_ATOMIC_OPS || ! defined HAVE_ASM_INLINE_MEMBAR

-

-#include "atomic/atomic_unknown.h"

-

-#endif /* if HAVE_ASM_INLINE_ATOMIC_OPS */

-

-#endif

@@ -1,6 +1,4 @@

 /* 

- * $Id$

- * 

  * Copyright (C) 2006 iptelorg GmbH

  *

  * Permission to use, copy, modify, and distribute this software for any

@@ -18,13 +16,14 @@

 /*!

  * \file

- * \brief SIP-router core :: Atomic operations and memory barriers

+ * \brief Kamailio core :: Atomic operations and memory barriers

+ * Copyright (C) 2006 iptelorg GmbH

  * \ingroup core

  * Module: \ref core

  * See \ref atomic

  */

-/*

+/**

  * \page atomicops  Atomic operations and memory barriers

  *

  *  WARNING: atomic ops do not include memory barriers

@@ -21,7 +21,7 @@

  * \brief SIP-router core :: Atomic operations and memory barriers

  * \ingroup core

  * Module: \ref core

- * See \ref atomicops

+ * See \ref atomic

  */

 /*

@@ -175,7 +175,7 @@

 #include "atomic/atomic_native.h"

-/* if no native operations, emulate them using locks */

+/*! \brief if no native operations, emulate them using locks */

 #if  ! defined HAVE_ASM_INLINE_ATOMIC_OPS || ! defined HAVE_ASM_INLINE_MEMBAR

 #include "atomic/atomic_unknown.h"

@@ -15,8 +15,18 @@

  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF

  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.

  */

+

+/*!

+ * \file

+ * \brief SIP-router core :: Atomic operations and memory barriers

+ * \ingroup core

+ * Module: \ref core

+ * See \ref atomicops

+ */

+

 /*

- *  atomic operations and memory barriers

+ * \page atomicops  Atomic operations and memory barriers

+ *

  *  WARNING: atomic ops do not include memory barriers

  *  

  *  memory barriers:

@@ -22,9 +22,15 @@

  *  memory barriers:

  *  ----------------

  *

- *  void membar();       - memory barrier (load & store)

- *  void membar_read()   - load (read) memory barrier

- *  void membar_write()  - store (write) memory barrier

+ *  void membar();        - memory barrier (load & store)

+ *  void membar_read()    - load (read) memory barrier

+ *  void membar_write()   - store (write) memory barrier

+ *  void membar_depends() - read depends memory barrier, needed before using

+ *                          the contents of a pointer (for now is needed only

+ *                          on Alpha so on all other CPUs it will be a no-op)

+ *                          For more info see: 

+ *                          http://lse.sourceforge.net/locking/wmbdd.html

+ *                          http://www.linuxjournal.com/article/8212

  *

  *  void membar_enter_lock() - memory barrier function that should be 

  *                             called after a lock operation (where lock is

@@ -44,6 +50,37 @@

  *                             Example: raw_lock(l); membar_enter_lock(); ..

  *                                      ... critical section ...

  *                                      membar_leave_lock(); raw_unlock(l);

+ *  void membar_atomic_op() - memory barrier that should be called if a memory

+ *                            barrier is needed immediately after or 

+ *                            immediately before an atomic operation

+ *                            (for example: atomic_inc(&i); membar_atomic_op()

+ *                               instead of atomic_inc(&i); membar()).

+ *                            atomic_op means every atomic operation except get

+ *                            and set (for them use membar_atomic_setget()).

+ *                            Using membar_atomic_op() instead of membar() in

+ *                            these cases will generate faster code on some

+ *                            architectures (for now x86 and x86_64), where 

+ *                            atomic operations act also as memory barriers.

+ *                            Note that mb_atomic_<OP>(...) is equivalent to

+ *                            membar_atomic_op(); atomic_<OP>(...) and in this

+ *                            case the first form is preferred).

+ * void membar_atomic_setget() - same as above but for atomic_set and 

+ *                            atomic_get (and not for any other atomic op.,

+ *                            including atomic_get_and_set, for them use

+ *                            membar_atomic_op()).

+ *                            Note that mb_atomic_{get,set}(&i) is equivalent 

+ *                            and preferred to membar_atomic_setget(); 

+ *                            atomic_{get,set}(&i) (it will generate faster

+ *                            code on x86 and x86_64).

+ * void membar_read_atomic_op() - like membar_atomic_op(), but acts only as

+ *                             a read barrier.

+ * void membar_read_atomic_setget() - like membar_atomic_setget() but acts only

+ *                            as a read barrier.

+ * void membar_write_atomic_op() - like membar_atomic_op(), but acts only as

+ *                            a write barrier.

+ * void membar_write_atomic_setget() - like membar_atomic_setget() but acts 

+ *                            only as a write barrier.

+ *

  *

  *  Note: - properly using memory barriers is tricky, in general try not to 

  *        depend on them. Locks include memory barriers, so you don't need

@@ -67,6 +104,10 @@

  *  int atomic_dec_and_test(atomic_t* v)     - returns 1 if the result is 0

  *  void atomic_or (atomic_t* v, int mask)   - v->val|=mask 

  *  void atomic_and(atomic_t* v, int mask)   - v->val&=mask

+ *  int atomic_add(atomic_t* v, int i)       - v->val+=i; return v->val

+ *  int atomic_cmpxchg(atomic_t* v, o, n)    - r=v->val; if (r==o) v->val=n;

+ *                                             return r (old value)

+ *

  * 

  * same ops, but with builtin memory barriers:

  *

@@ -79,6 +120,9 @@

  *  int mb_atomic_dec_and_test(atomic_t* v)  - returns 1 if the result is 0

  *  void mb_atomic_or(atomic_t* v, int mask - v->val|=mask 

  *  void mb_atomic_and(atomic_t* v, int mask)- v->val&=mask

+ *  int mb_atomic_add(atomic_t* v, int i)    - v->val+=i; return v->val

+ *  int mb_atomic_cmpxchg(atomic_t* v, o, n) - r=v->val; if (r==o) v->val=n;

+ *                                             return r (old value)

  *

  *  Same operations are available for int and long. The functions are named

  *   after the following rules:

@@ -26,9 +26,31 @@

  *  void membar_read()   - load (read) memory barrier

  *  void membar_write()  - store (write) memory barrier

  *

- *  Note: properly using memory barriers is tricky, in general try not to 

+ *  void membar_enter_lock() - memory barrier function that should be 

+ *                             called after a lock operation (where lock is

+ *                             an asm inline function that uses atomic store

+ *                             operation on the lock var.). It is at most

+ *                             a StoreStore|StoreLoad barrier, but could also

+ *                             be empty if an atomic op implies a memory 

+ *                             barrier on the specific arhitecture.

+ *                             Example usage: 

+ *                               raw_lock(l); membar_enter_lock(); ...

+ *  void membar_leave_lock() - memory barrier function that should be called 

+ *                             before an unlock operation (where unlock is an

+ *                             asm inline function that uses at least an atomic

+ *                             store to on the lock var.). It is at most a 

+ *                             LoadStore|StoreStore barrier (but could also be

+ *                             empty, see above).

+ *                             Example: raw_lock(l); membar_enter_lock(); ..

+ *                                      ... critical section ...

+ *                                      membar_leave_lock(); raw_unlock(l);

+ *

+ *  Note: - properly using memory barriers is tricky, in general try not to 

  *        depend on them. Locks include memory barriers, so you don't need

  *        them for writes/load already protected by locks.

+ *        - membar_enter_lock() and membar_leave_lock() are needed only if

+ *        you implement your own locks using atomic ops (ser locks have the

+ *        membars included)

  *

  * atomic operations:

  * ------------------

@@ -89,70 +111,17 @@

  * History:

  * --------

  *  2006-03-08  created by andrei

+ *  2007-05-13  moved some of the decl. and includes into atomic_common.h and 

+ *               atomic_native.h (andrei)

  */

 #ifndef __atomic_ops

 #define __atomic_ops

-/* atomic_t defined as a struct to easily catch non atomic ops. on it,

- * e.g.  atomic_t  foo; foo++  will generate a compile error */

-typedef struct{ volatile int val; } atomic_t; 

-

-

-/* store and load operations are atomic on all cpus, note however that they

- * don't include memory barriers so if you want to use atomic_{get,set} 

- * to implement mutexes you must use the mb_* versions or explicitely use

- * the barriers */

-

-#define atomic_set_int(pvar, i) (*(pvar)=i)

-#define atomic_set_long(pvar, i) (*(pvar)=i)

-#define atomic_get_int(pvar) (*(pvar))

-#define atomic_get_long(pvar) (*(pvar))

-

-#define atomic_set(at_var, value)	(atomic_set_int(&((at_var)->val), (value)))

-

-inline static int atomic_get(atomic_t *v)

-{

-	return atomic_get_int(&(v->val));

-}

-

-

-

-#ifdef CC_GCC_LIKE_ASM

-

-#if defined __CPU_i386 || defined __CPU_x86_64

-

-#include "atomic/atomic_x86.h"

-

-#elif defined __CPU_mips2 || defined __CPU_mips64 || \

-	  ( defined __CPU_mips && defined MIPS_HAS_LLSC )

-

-#include "atomic/atomic_mips2.h"

-

-#elif defined __CPU_ppc || defined __CPU_ppc64

-

-#include "atomic/atomic_ppc.h"

-

-#elif defined __CPU_sparc64

-

-#include "atomic/atomic_sparc64.h"

-

-#elif defined __CPU_sparc

-

-#include "atomic/atomic_sparc.h"

-

-#elif defined __CPU_arm || defined __CPU_arm6

-

-#include "atomic/atomic_arm.h"

-

-#elif defined __CPU_alpha

-

-#include "atomic/atomic_alpha.h"

-

-#endif /* __CPU_xxx  => no known cpu */

-

-#endif /* CC_GCC_LIKE_ASM */

+#include "atomic/atomic_common.h"

+#include "atomic/atomic_native.h"

+/* if no native operations, emulate them using locks */

 #if  ! defined HAVE_ASM_INLINE_ATOMIC_OPS || ! defined HAVE_ASM_INLINE_MEMBAR

 #include "atomic/atomic_unknown.h"

@@ -3,26 +3,17 @@

  * 

  * Copyright (C) 2006 iptelorg GmbH

  *

- * This file is part of ser, a free SIP server.

+ * Permission to use, copy, modify, and distribute this software for any

+ * purpose with or without fee is hereby granted, provided that the above

+ * copyright notice and this permission notice appear in all copies.

  *

- * ser is free software; you can redistribute it and/or modify

- * it under the terms of the GNU General Public License as published by

- * the Free Software Foundation; either version 2 of the License, or

- * (at your option) any later version

- *

- * For a license to use the ser software under conditions

- * other than those described here, or to purchase support for this

- * software, please contact iptel.org by e-mail at the following addresses:

- *    info@iptel.org

- *

- * ser is distributed in the hope that it will be useful,

- * but WITHOUT ANY WARRANTY; without even the implied warranty of

- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

- * GNU General Public License for more details.

- *

- * You should have received a copy of the GNU General Public License

- * along with this program; if not, write to the Free Software

- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA

+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES

+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF

+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR

+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES

+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN

+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF

+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.

  */

 /*

  *  atomic operations and memory barriers

@@ -86,11 +86,13 @@

  *                            safe

  *                   __CPU_i386, __CPU_x86_64, X86_OOSTORE - see 

  *                       atomic/atomic_x86.h

- *                   __CPU_mips, __CPU_mip2, __CPU_mip64, MIPS_HAS_LLSC - see

+ *                   __CPU_mips, __CPU_mips2, __CPU_mips64, MIPS_HAS_LLSC - see

  *                       atomic/atomic_mip2.h

  *                   __CPU_ppc, __CPU_ppc64 - see atomic/atomic_ppc.h

  *                   __CPU_sparc - see atomic/atomic_sparc.h

  *                   __CPU_sparc64, SPARC64_MODE - see atomic/atomic_sparc64.h

+ *                   __CPU_arm, __CPU_arm6 - see atomic/atomic_arm.h

+ *                   __CPU_alpha - see atomic/atomic_alpha.h

  */

 /* 

  * History:

@@ -147,6 +149,14 @@ inline static int atomic_get(atomic_t *v)

 #include "atomic/atomic_sparc.h"

+#elif defined __CPU_arm || defined __CPU_arm6

+

+#include "atomic/atomic_arm.h"

+

+#elif defined __CPU_alpha

+

+#include "atomic/atomic_alpha.h"

+

 #endif /* __CPU_xxx  => no known cpu */

 #endif /* CC_GCC_LIKE_ASM */

@@ -45,26 +45,52 @@

  *

  * not including memory barriers:

  *

- *  void atomic_set(atomic_t* v, long i)      -      v->val=i

- *  long atomic_get(atomic_t* v)              -       return v->val

+ *  void atomic_set(atomic_t* v, int i)      - v->val=i

+ *  int atomic_get(atomic_t* v)              - return v->val

+ *  int atomic_get_and_set(atomic_t *v, i)   - return old v->val, v->val=i

  *  void atomic_inc(atomic_t* v)

  *  void atomic_dec(atomic_t* v)

- *  long atomic_inc_and_test(atomic_t* v)     - returns 1 if the result is 0

- *  long atomic_dec_and_test(atomic_t* v)     - returns 1 if the result is 0

- *  void atomic_or (atomic_t* v, long mask)   - v->val|=mask 

- *  void atomic_and(atomic_t* v, long mask)   - v->val&=mask

+ *  int atomic_inc_and_test(atomic_t* v)     - returns 1 if the result is 0

+ *  int atomic_dec_and_test(atomic_t* v)     - returns 1 if the result is 0

+ *  void atomic_or (atomic_t* v, int mask)   - v->val|=mask 

+ *  void atomic_and(atomic_t* v, int mask)   - v->val&=mask

  * 

  * same ops, but with builtin memory barriers:

  *

- *  void mb_atomic_set(atomic_t* v, long i)      -      v->val=i

- *  long mb_atomic_get(atomic_t* v)              -       return v->val

+ *  void mb_atomic_set(atomic_t* v, int i)      -  v->val=i

+ *  int mb_atomic_get(atomic_t* v)              -  return v->val

+ *  int mb_atomic_get_and_set(atomic_t *v, i)   -  return old v->val, v->val=i

  *  void mb_atomic_inc(atomic_t* v)

  *  void mb_atomic_dec(atomic_t* v)

- *  long mb_atomic_inc_and_test(atomic_t* v)  - returns 1 if the result is 0

- *  long mb_atomic_dec_and_test(atomic_t* v)  - returns 1 if the result is 0

- *  void mb_atomic_or(atomic_t* v, long mask - v->val|=mask 

- *  void mb_atomic_and(atomic_t* v, long mask)- v->val&=mask

- * 

+ *  int mb_atomic_inc_and_test(atomic_t* v)  - returns 1 if the result is 0

+ *  int mb_atomic_dec_and_test(atomic_t* v)  - returns 1 if the result is 0

+ *  void mb_atomic_or(atomic_t* v, int mask - v->val|=mask 

+ *  void mb_atomic_and(atomic_t* v, int mask)- v->val&=mask

+ *

+ *  Same operations are available for int and long. The functions are named

+ *   after the following rules:

+ *     - add an int or long  suffix to the correspondent atomic function

+ *     -  volatile int* or volatile long* replace atomic_t* in the functions

+ *        declarations

+ *     -  long and int replace the parameter type (if the function has an extra

+ *        parameter) and the return value

+ *  E.g.:

+ *    long atomic_get_long(volatile long* v)

+ *    int atomic_get_int( volatile int* v)

+ *    long atomic_get_and_set(volatile long* v, long l)

+ *    int atomic_get_and_set(volatile int* v, int i)

+ *

+ * Config defines:   CC_GCC_LIKE_ASM  - the compiler support gcc style

+ *                     inline asm

+ *                   NOSMP - the code will be a little faster, but not SMP

+ *                            safe

+ *                   __CPU_i386, __CPU_x86_64, X86_OOSTORE - see 

+ *                       atomic/atomic_x86.h

+ *                   __CPU_mips, __CPU_mip2, __CPU_mip64, MIPS_HAS_LLSC - see

+ *                       atomic/atomic_mip2.h

+ *                   __CPU_ppc, __CPU_ppc64 - see atomic/atomic_ppc.h

+ *                   __CPU_sparc - see atomic/atomic_sparc.h

+ *                   __CPU_sparc64, SPARC64_MODE - see atomic/atomic_sparc64.h

  */

 /* 

  * History:

@@ -76,433 +102,59 @@

 /* atomic_t defined as a struct to easily catch non atomic ops. on it,

  * e.g.  atomic_t  foo; foo++  will generate a compile error */

-typedef struct{ volatile long val; } atomic_t; 

+typedef struct{ volatile int val; } atomic_t; 

 /* store and load operations are atomic on all cpus, note however that they

  * don't include memory barriers so if you want to use atomic_{get,set} 

- * to implement mutexes you must explicitely use the barriers */

-#define atomic_set(at_var, value)	((at_var)->val=(value))

-#define atomic_get(at_var) ((at_var)->val)

-

-/* init atomic ops */

-int atomic_ops_init();

-

-

-

-#if defined(__CPU_i386) || defined(__CPU_x86_64)

-

-#define HAVE_ASM_INLINE_ATOMIC_OPS

-

-#ifdef NOSMP

-#define __LOCK_PREF 

-#else

-#define __LOCK_PREF "lock ;"

-#endif

-

-

-/* memory barriers */

-

-#ifdef NOSMP

-

-#define membar()	asm volatile ("" : : : "memory")

-#define membar_read()	membar()

-#define membar_write()	membar()

+ * to implement mutexes you must use the mb_* versions or explicitely use

+ * the barriers */

-#else

+#define atomic_set_int(pvar, i) (*(pvar)=i)

+#define atomic_set_long(pvar, i) (*(pvar)=i)

+#define atomic_get_int(pvar) (*(pvar))

+#define atomic_get_long(pvar) (*(pvar))

-/* although most x86 do stores in order, we're playing it safe and use

- *  oostore ready write barriers */

-#define X86_OOSTORE 

+#define atomic_set(at_var, value)	(atomic_set_int(&((at_var)->val), (value)))

-/* membar: lfence, mfence, sfence available only on newer cpus, so for now

- * stick to lock addl */

-#define membar() \

-	asm volatile( \

-					" lock; addl $0, 0(%%esp) \n\t " \

-					: : : "memory" \

-				) 

-

-#define membar_read()	membar()

-

-#ifdef X86_OOSTORE

-/* out of order store version */

-#define membar_write()	membar()

-#else

-/* no oostore, most x86 cpus => do nothing, just a gcc do_not_cache barrier*/

-#define membar_write()	asm volatile ("" : : : "memory")

-#endif

-

-

-#endif /* NOSMP */

-

-

-#define atomic_inc(var) \

-	asm volatile( \

-			__LOCK_PREF " incl %0 \n\t"  \

-			: "=m"((var)->val) : "m"((var)->val) : "cc", "memory" \

-			) 

-

-#define atomic_dec(var) \

-	asm volatile( \

-			__LOCK_PREF " decl %0 \n\t" \

-			: "=m"((var)->val) : "m"((var)->val) : "cc", "memory" \

-			) 

-

-#define atomic_and(var, i) \

-	asm volatile( \

-			__LOCK_PREF " andl %1, %0 \n\t" \

-			: "=m"((var)->val) : "ri"((i)), "m"((var)->val) : "cc", "memory" \

-			)

-#define atomic_or(var, i) \

-	asm volatile( \

-			__LOCK_PREF " orl %1, %0 \n\t" \

-			: "=m"((var)->val) : "ri"((i)), "m"((var)->val) : "cc", "memory" \

-			)

-

-

-/* returns 1 if the result is 0 */

-inline static long atomic_inc_and_test(atomic_t* var)

+inline static int atomic_get(atomic_t *v)

 {

-	char ret;

-	

-	asm volatile(

-			__LOCK_PREF " incl %0 \n\t"

-			"setz  %1 \n\t"

-			: "=m"(var->val), "=qm"(ret) : "m" (var->val) : "cc", "memory"

-			);

-	return ret;

+	return atomic_get_int(&(v->val));

 }

-/* returns 1 if the result is 0 */

-inline static long atomic_dec_and_test(atomic_t* var)

-{

-	char ret;

-	

-	asm volatile(

-			__LOCK_PREF " decl %0 \n\t"

-			"setz  %1 \n\t"

-			: "=m"(var->val), "=qm"(ret) : "m" (var->val) : "cc", "memory"

-			);

-	return ret;

-}

-

-#ifdef NOSMP

-

-#define mb_atomic_set(v, i) \

-	do{ \

-		membar(); \

-		atomic_set(v, i); \

-	}while(0)

-

-

-inline static long mb_atomic_get(atomic_t* v)

-{

-	membar();

-	return atomic_get(v);

-}

-#else /* NOSMP */

-

-

-inline static void mb_atomic_set(atomic_t* v, long i)

-{

-	asm volatile(

-			"xchgl %1, %0 \n\t"

-			: "+q"(i), "=m"(v->val) : "m"((v)->val) : "memory" 

-			);

-}

-

-

-

-inline static long mb_atomic_get(atomic_t* var)

-{

-	long ret;

-	

-	asm volatile(

-			__LOCK_PREF " cmpxchg %0, %1 \n\t"

-			: "=a"(ret)  : "m"(var->val) : "cc", "memory"

-			);

-	return ret;

-}

-

-#endif /* NOSMP */

-

-

-/* on x86 atomic intructions act also as barriers */

-#define mb_atomic_inc(v)	atomic_inc(v)

-#define mb_atomic_dec(v)	atomic_dec(v)

-#define mb_atomic_or(v, m)	atomic_or(v, m)

-#define mb_atomic_and(v, m)	atomic_and(v, m)

-#define mb_atomic_inc_and_test(v)	atomic_inc_and_test(v)

-#define mb_atomic_dec_and_test(v)	atomic_dec_and_test(v)

-

-

-#elif defined __CPU_mips2 || ( defined __CPU_mips && defined MIPS_HAS_LLSC )

-

-#define HAVE_ASM_INLINE_ATOMIC_OPS

-

-#ifdef NOSMP

-#define membar() asm volatile ("" : : : "memory") /* gcc do not cache barrier*/

-#define membar_read()  membar()

-#define membar_write() membar()

-#else

-

-#define membar() \

-	asm volatile( \

-			".set push \n\t" \

-			".set noreorder \n\t" \

-			".set mips2 \n\t" \

-			"    sync\n\t" \

-			".set pop \n\t" \

-			: : : "memory" \

-			) 

-

-#define membar_read()  membar()

-#define membar_write() membar()

-

-#endif /* NOSMP */

-

+#ifdef CC_GCC_LIKE_ASM

-/* main asm block */

-#define ATOMIC_ASM_OP(op) \

-			".set push \n\t" \

-			".set noreorder \n\t" \

-			".set mips2 \n\t" \

-			"1:   ll %1, %0 \n\t" \

-			"     " op "\n\t" \

-			"     sc %2, %0 \n\t" \

-			"     beqz %2, 1b \n\t" \

-			"     nop \n\t" \

-			".set pop \n\t" 

+#if defined __CPU_i386 || defined __CPU_x86_64

+#include "atomic/atomic_x86.h"

-#define ATOMIC_FUNC_DECL(NAME, OP, RET_TYPE, RET_EXPR) \

-	inline static RET_TYPE atomic_##NAME (atomic_t *var) \

-	{ \

-		long ret, tmp; \

-		asm volatile( \

-			ATOMIC_ASM_OP(OP) \

-			: "=m"((var)->val), "=&r"(ret), "=&r"(tmp)  \

-			: "m"((var)->val) \

-			 \

-			); \

-		return RET_EXPR; \

-	}

+#elif defined __CPU_mips2 || defined __CPU_mips64 || \

+	  ( defined __CPU_mips && defined MIPS_HAS_LLSC )

+#include "atomic/atomic_mips2.h"

-/* same as above, but with CT in %3 */

-#define ATOMIC_FUNC_DECL_CT(NAME, OP, CT, RET_TYPE, RET_EXPR) \

-	inline static RET_TYPE atomic_##NAME (atomic_t *var) \

-	{ \

-		long ret, tmp; \

-		asm volatile( \

-			ATOMIC_ASM_OP(OP) \

-			: "=m"((var)->val), "=&r"(ret), "=&r"(tmp)  \

-			: "r"((CT)), "m"((var)->val) \

-			 \

-			); \

-		return RET_EXPR; \

-	}

+#elif defined __CPU_ppc || defined __CPU_ppc64

+#include "atomic/atomic_ppc.h"

-/* takes an extra param, i which goes in %3 */

-#define ATOMIC_FUNC_DECL1(NAME, OP, RET_TYPE, RET_EXPR) \

-	inline static RET_TYPE atomic_##NAME (atomic_t *var, long i) \

-	{ \

-		long ret, tmp; \

-		asm volatile( \

-			ATOMIC_ASM_OP(OP) \

-			: "=m"((var)->val), "=&r"(ret), "=&r"(tmp)  \

-			: "r"((i)), "m"((var)->val) \

-			 \

-			); \

-		return RET_EXPR; \

-	}

+#elif defined __CPU_sparc64

+#include "atomic/atomic_sparc64.h"

-ATOMIC_FUNC_DECL(inc,      "addiu %2, %1, 1", void, /* no return */ )

-ATOMIC_FUNC_DECL(inc_and_test, "addiu %2, %1, 1", long, (ret+1)==0 )

-

-ATOMIC_FUNC_DECL_CT(dec,   "subu %2, %1, %3", 1,  void, /* no return */ )

-ATOMIC_FUNC_DECL_CT(dec_and_test, "subu %2, %1, %3", 1, long, (ret-1)==0 )

-

-ATOMIC_FUNC_DECL1(and, "and %2, %1, %3", void, /* no return */ )

-ATOMIC_FUNC_DECL1(or,  "or  %2, %1, %3", void,  /* no return */ )

-

-

-/* with integrated membar */

-

-#define mb_atomic_set(v, i) \

-	do{ \

-		membar(); \

-		atomic_set(v, i); \

-	}while(0)

-

-

-

-inline static long mb_atomic_get(atomic_t* v)

-{