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- timer: proper includes for no fast lock case - Makefile: mips gcc params fixes - atomic_* updates [work in progress]

Andrei Pelinescu-Onciul authored on 13/03/2006 20:20:48
Showing 5 changed files
... ...
@@ -726,27 +726,26 @@ ifeq	($(ARCH), mips)
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 		# if gcc 
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 ifeq		($(CC_NAME), gcc)
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 				#common stuff
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-				CFLAGS=-O9 -funroll-loops  -Wcast-align $(PROFILE) \
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+				CFLAGS=-O9 -funroll-loops  $(PROFILE) \
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 					-Wall 
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 			#if gcc 4.0+
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 ifeq			($(CC_SHORTVER), 4.x)
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-					CFLAGS+=-mcpu=r3000 -minline-all-stringops \
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+					CFLAGS+=-march=r3000 -minline-all-stringops \
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 							-ftree-vectorize
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 else
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 			#if gcc 3.4+
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 ifeq			($(CC_SHORTVER), 3.4)
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-					CFLAGS+= -mcpu=r3000
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+					CFLAGS+= -march=r3000
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 else
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 			#if gcc 3.0
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 ifeq			($(CC_SHORTVER), 3.0)
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-					CFLAGS+= -mcpu=r3000
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-							#-mcpu=athlon
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+					CFLAGS+= -march=r3000
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 else
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 ifeq			($(CC_SHORTVER), 2.9x) #older gcc version (2.9[1-5])
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 $(warning 			Old gcc detected ($(CC_SHORTVER)), use  gcc 3.0.x \
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 					for better results)
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-					CFLAGS+=-mcpu=r3000
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+					CFLAGS+=-march=r3000
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 else
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 				#really old version
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 $(warning			You are using an old and unsupported gcc \
... ...
@@ -36,7 +36,7 @@
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 #include "atomic_ops.h"
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 #ifdef ATOMIC_USE_LOCK
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-gen_lock_t* atomic_lock;
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+gen_lock_t* _atomic_lock;
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 #endif
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42 42
 
... ...
@@ -47,14 +47,14 @@ int atomic_ops_init()
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 	ret=0;
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 #ifdef ATOMIC_USE_LOCK
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-	if ((atomic_lock=lock_alloc())==0){
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+	if ((_atomic_lock=lock_alloc())==0){
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 		ret=-1;
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 		goto end;
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 	}
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-	if (lock_init(atomic_lock)==0){
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+	if (lock_init(_atomic_lock)==0){
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 		ret=-1;
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-		lock_destroy(atomic_lock);
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-		atomic_lock=0;
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+		lock_destroy(_atomic_lock);
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+		_atomic_lock=0;
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 		goto end;
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 	}
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 end:
... ...
@@ -43,6 +43,8 @@
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  * ------------------
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  *  type: atomic_t
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  *
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+ * not including memory barriers:
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+ *
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  *  void atomic_set(atomic_t* v, long i)      -      v->val=i
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  *  long atomic_get(atomic_t* v)              -       return v->val
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  *  void atomic_inc(atomic_t* v)
... ...
@@ -51,7 +53,18 @@
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  *  long atomic_dec_and_test(atomic_t* v)     - returns 1 if the result is 0
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  *  void atomic_or (atomic_t* v, long mask)   - v->val|=mask 
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  *  void atomic_and(atomic_t* v, long mask)   - v->val&=mask
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- *  
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+ * 
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+ * same ops, but with builtin memory barriers:
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+ *
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+ *  void mb_atomic_set(atomic_t* v, long i)      -      v->val=i
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+ *  long mb_atomic_get(atomic_t* v)              -       return v->val
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+ *  void mb_atomic_inc(atomic_t* v)
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+ *  void mb_atomic_dec(atomic_t* v)
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+ *  long mb_atomic_inc_and_test(atomic_t* v)  - returns 1 if the result is 0
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+ *  long mb_atomic_dec_and_test(atomic_t* v)  - returns 1 if the result is 0
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+ *  void mb_atomic_or(atomic_t* v, long mask - v->val|=mask 
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+ *  void mb_atomic_and(atomic_t* v, long mask)- v->val&=mask
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+ * 
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  */
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 /* 
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  * History:
... ...
@@ -79,6 +92,8 @@ int atomic_ops_init();
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 #if defined(__CPU_i386) || defined(__CPU_x86_64)
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+#define HAVE_ASM_INLINE_ATOMIC_OPS
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+
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 #ifdef NOSMP
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 #define __LOCK_PREF 
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 #else
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@@ -86,14 +101,13 @@ int atomic_ops_init();
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 #endif
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88 88
 
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-
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 /* memory barriers */
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 #ifdef NOSMP
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-#define membar()
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-#define membar_read()
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-#define membar_write()
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+#define membar()	asm volatile ("" : : : "memory")
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+#define membar_read()	membar()
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+#define membar_write()	membar()
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 #else
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... ...
@@ -101,7 +115,7 @@ int atomic_ops_init();
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  *  oostore ready write barriers */
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 #define X86_OOSTORE 
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-/* membar, mfence, lfence, sfence available only on newer cpus, so for now
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+/* membar: lfence, mfence, sfence available only on newer cpus, so for now
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  * stick to lock addl */
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 #define membar() \
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 	asm volatile( \
... ...
@@ -115,7 +129,7 @@ int atomic_ops_init();
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 /* out of order store version */
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 #define membar_write()	membar()
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 #else
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-/* no oostore, most x86 cpus => do no thing, just a gcc do_not_cache barrier*/
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+/* no oostore, most x86 cpus => do nothing, just a gcc do_not_cache barrier*/
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 #define membar_write()	asm volatile ("" : : : "memory")
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 #endif
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... ...
@@ -177,8 +191,10 @@ inline static long atomic_dec_and_test(atomic_t* var)
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 #elif defined __CPU_mips2
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+#define HAVE_ASM_INLINE_ATOMIC_OPS
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+
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 #ifdef NOSMP
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-#define membar()
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+#define membar() asm volatile ("" : : : memory) /* gcc do not cache barrier*/
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 #define membar_read()  membar()
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 #define membar_write() membar()
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 #else
... ...
@@ -262,34 +278,32 @@ ATOMIC_FUNC_DECL_CT(dec_and_test, "subu %2, %1, %3", 1, long, (ret-1)==0 )
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 ATOMIC_FUNC_DECL1(and, "and %2, %1, %3", void, /* no return */ )
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 ATOMIC_FUNC_DECL1(or,  "or  %2, %1, %3", void,  /* no return */ )
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-#else /* no known cpu */
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+#endif /* __CPU_xxx  => no known cpu */
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+
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+
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+#ifndef HAVE_ASM_INLINE_ATOMIC_OPS
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 #include "locking.h"
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 #define ATOMIC_USE_LOCK
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-extern gen_lock_t* atomic_lock;
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+extern gen_lock_t* _atomic_lock;
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273 276
 
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+#define atomic_lock    lock_get(_atomic_lock)
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+#define atomic_unlock  lock_release(_atomic_lock)
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-#ifdef NOSMP
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-#define smp_atomic_lock
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-#define smp_atomic_unlock
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-#else
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-#define smp_atomic_lock    lock_get(atomic_lock)
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-#define smp_atomic_unlock  lock_release(atomic_lock)
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-#endif
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283 281
 /* memory barriers 
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  *  not a known cpu -> fall back lock/unlock: safe but costly  (it should 
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  *  include a memory barrier effect) */
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-
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 #define membar() \
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 	do{\
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-		smp_atomic_lock; \
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-		smp_atomic_unlock; \
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+		atomic_lock; \
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+		atomic_unlock; \
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 	} while(0)
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290
+
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 #define membar_write() membar()
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 #define membar_read()  membar()
... ...
@@ -299,32 +313,32 @@ extern gen_lock_t* atomic_lock;
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 #define atomic_inc(var) \
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 	do{ \
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-		smp_atomic_lock; \
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+		atomic_lock; \
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 		(var)->val++;\
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-		smp_atomic_unlock;\
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+		atomic_unlock;\
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 	}while(0)
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307 307
 
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 #define atomic_dec(var) \
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 	do{ \
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-		smp_atomic_lock; \
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+		atomic_lock; \
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 		(var)->val--; \
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-		smp_atomic_unlock; \
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+		atomic_unlock; \
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 	}while(0)
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315 315
 
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 #define atomic_and(var, i) \
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 	do{ \
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-		smp_atomic_lock; \
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+		atomic_lock; \
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 		(var)->val&=i; \
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-		smp_atomic_unlock; \
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+		atomic_unlock; \
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 	}while(0)
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 #define atomic_or(var, i) \
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 	do{ \
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-		smp_atomic_lock; \
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+		atomic_lock; \
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 		(var)->val|=i; \
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-		smp_atomic_unlock; \
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+		atomic_unlock; \
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 	}while(0)
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330 330
 
... ...
@@ -334,10 +348,10 @@ inline static long atomic_inc_and_test(atomic_t* var)
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 {
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 	long ret;
336 336
 	
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-	smp_atomic_lock;
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+	atomic_lock;
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 	var->val++;
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 	ret=var->val;
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-	smp_atomic_unlock;
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+	atomic_unlock;
341 341
 	
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 	return (ret==0);
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 }
... ...
@@ -348,15 +362,39 @@ inline static long atomic_dec_and_test(atomic_t* var)
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 {
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 	long ret;
350 350
 	
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-	smp_atomic_lock;
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+	atomic_lock;
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 	var->val++;
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 	ret=var->val;
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-	smp_atomic_unlock;
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+	atomic_unlock;
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 	return (ret==0);
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 }
358 358
 
359 359
 
360
-#endif /* if __CPU_xx */
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+/* memory barrier versions, the same as "normal" versions, except fot
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+ * the set/get
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+ * (the * atomic_lock/unlock part should act as a barrier)
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+ */
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+
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+#define mb_atomic_set(v, i) \
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+	do{ \
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+		membar(); \
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+		atomic_set(v, i); \
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+	}while(0)
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+
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+#define mb_atomic_get(v) \
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+	do{ \
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+		membar(); \
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+		atomic_get(v); \
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+	}while(0)
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+
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+#define mb_atomic_inc(v)	atomic_inc(v)
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+#define mb_atomic_dec(v)	atomic_dec(v)
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+#define mb_atomic_or(v, m)	atomic_or(v, m)
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+#define mb_atomic_and(v, m)	atomic_and(v, m)
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+#define mb_atomic_inc_and_test(v)	atomic_inc_and_test(v)
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+#define mb_atomic_dec_and_test(v)	atomic_dec_and_test(v)
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+
384
+#endif /* if HAVE_ASM_INLINE_ATOMIC_OPS */
361 385
 
362 386
 #endif
... ...
@@ -1,7 +1,7 @@
1 1
 /*
2 2
  *
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  *  simple atomic ops testing program
4
- *  (no paralles stuff)
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+ *  (no paralel stuff, just see if the opcodes are "legal")
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  * 
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  *  Compile with: gcc -D__CPU_i386 -O3 on x86 machines and
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  *                gcc -mips2 -O2 -D__CPU_mips2  on mips machines.
... ...
@@ -56,6 +56,15 @@
56 56
 #endif
57 57
 #include "locking.h"
58 58
 
59
+#ifdef HAVE_SCHED_YIELD
60
+#include <sched.h>
61
+#else
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+#include <unistd.h>
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+	/* fake sched_yield */
64
+#ifndef sched_yield()
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+#define sched_yield()	sleep(0)
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+#endif
67
+#endif
59 68
 
60 69
 
61 70